| Reference |
ISO/IEC 13961 ed1.0 withdrawn corrigendum |
> preview
|
| Title |
Information technology - Scalable Coherent Interface (SCI)
|
| Publication date |
2000-07-31 |
Format, price
(Swiss francs)
and language |
 | 238.- |
| 265 pages |  | 238.- |
| 7253 Kb |
|
| |
| Abstract |
The scalable coherent interface (SCI) provides computer-bus-like services but,
instead of a bus, uses a collection of fast point-to-point unidirectional links to provide the far
higher throughput needed for high-performance multiprocessor systems. SCI supports
distributed, shared memory with optional cache coherence for tightly coupled systems, and
message-passing for loosely coupled systems. Initial SCI links are defined at 1 Gbyte/s (16-bit
parallel) and 1 Gb/s (serial). For applications requiring modular packaging, an interchangeable
module is specified along with connector and power. The packets and protocols that implement
transactions are defined and their formal specification is provided in the form of computer
programs. In addition to the usual read-and-write transactions, SCI supports efficient
multiprocessor lock transactions. The distributed cache-coherence protocols are efficient and
can recover from an arbitrary number of transmission failures. SCI protocols ensure forward
progress despite multiprocessor conflicts (no deadlocks or starvation).
|
| Technical Committee |
JTC 1/SC 25 - Interconnection of information technology equipment
|
| ICS Codes |
| 35.160 |
Microprocessor systems
*Including PCs, calculators, etc.
*Integrated circuits, see 31.200 |
|
| |
| Replaced by |
|
| Stability date |
2011 |
| |
| Work in progress |
| Project | Stage code | Forecast publication date |
|---|
| No project under development | - | - |
|
Search
Quick access by ref. number
Basket
Payment
Just Published
Bestsellers