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Publication detail

 
Reference ISO/IEC 18372 ed1.0 withdrawn corrigendum
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Title Information technology - RapidIO TM interconnect specification
Publication date 2004-12-15
Format, price
(Swiss francs)
and language
198.- 399 pages
198.- 2248 Kb
 
Abstract The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.
Technical Committee JTC 1/SC 25 - Interconnection of information technology equipment  RSS
ICS Codes
35.200 Interface and interconnection equipment
 
Replaced by
Stability date 2014
 
Work in progress
ProjectStage codeForecast publication date
ISO/IEC 18372 Ed.2  CANn/a


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