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Reference IEC 62530 ed2.0 withdrawn corrigendum
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Title SystemVerilog - Unified Hardware Design, Specification, and Verification Language
Publication date 2011-05-19
Format, price
(Swiss francs)
and language
340.- 1251 pages
340.- 9891 Kb
Abstract IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.
Technical Committee 91 - Electronics assembly technology  RSS
ICS Codes
25.040 Industrial automation systems
*IT applications in industry, see 35.240.50
Replaced by
Stability date 2016
Work in progress
ProjectStage codeForecast publication date
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