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IEC 63011-1

IEC 63011-1:2018
Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
BASE PUBLICATION
English/French

Technical committee

TC 47/SC 47A Integrated circuits
Publication typeInternational Standard
Publication date2018-11-28
Edition1.0
ICS

31.200

Stability date2029
ISBN number9782832262900
Pages24
File size1.27 MB
EditionDatePublicationEditionStatus
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