IEC 60749-15 Redline version
IEC 60749-15:2020 RLV
Semiconductor devices - Mechanical and climatic test methods - Part 15: Resistance to soldering temperature for through-hole mounted devices
IEC 60749-15:2020 RLV contains both the official IEC International Standard and its Redline version. The Redline version is available in English only and provides you with a quick and easy way to compare all the changes between the official IEC Standard and its previous edition.
IEC 60749-15:2020 describes a test used to determine whether encapsulated solid state devices used for through-hole mounting can withstand the effects of the temperature to which they are subjected during soldering of their leads by using wave soldering. In order to establish a standard test procedure for the most reproducible methods, the solder dip method is used because of its more controllable conditions. This procedure determines whether devices are capable of withstanding the soldering temperature encountered in printed wiring board assembly operations, without degrading their electrical characteristics or internal connections. This test is destructive and may be used for qualification, lot acceptance and as a product monitor. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. This procedure does not simulate wave soldering or reflow heat exposure on the same side of the board as the package body. This edition includes the following significant technical changes with respect to the previous edition:
- inclusion of new Clause 3, Terms and definitions;
- clarification of the use of a soldering iron for producing the heating effect;
- inclusion an option to use accelerated ageing.
IEC 60749-15:2020 describes a test used to determine whether encapsulated solid state devices used for through-hole mounting can withstand the effects of the temperature to which they are subjected during soldering of their leads by using wave soldering. In order to establish a standard test procedure for the most reproducible methods, the solder dip method is used because of its more controllable conditions. This procedure determines whether devices are capable of withstanding the soldering temperature encountered in printed wiring board assembly operations, without degrading their electrical characteristics or internal connections. This test is destructive and may be used for qualification, lot acceptance and as a product monitor. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. This procedure does not simulate wave soldering or reflow heat exposure on the same side of the board as the package body. This edition includes the following significant technical changes with respect to the previous edition:
- inclusion of new Clause 3, Terms and definitions;
- clarification of the use of a soldering iron for producing the heating effect;
- inclusion an option to use accelerated ageing.
CHF 52.-
Technical committee
TC 47 Semiconductor devicesPublication type | International Standard |
Publication date | 2020-07-14 |
Edition | 3.0 |
ICS | 31.080.01 |
Stability date | 2030 |
ISBN number | 9782832286869 |
Pages | 27 |
File size | 1.05 MB |
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