IEC 61523-1
IEC 61523-1:2023
Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the “delay calculation language” (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the “delay calculation language” (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.
CHF 450.-
Technical committee
TC 91 Electronics assembly technology| Publication type | International Standard |
| Publication date | 2023-10-11 |
| Edition | 3.0 |
| ICS | 25.040.01 35.060 |
| Stability date | 2028 |
| ISBN number | 9782832275399 |
| Pages | 640 |
| File size | 6.18 MB |
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