ISO/IEC 18372:2004 

Information technology - RapidIO TM interconnect specification

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Abstract

The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.

The electronic version of this International Standard can be downloaded from the ISO/IEC Information Technology Task Force (ITTF) website.

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Additional information

Publication typeInternational Standard
Publication date2004-12-15
Edition1.0
Available language(s)English
TC/SCISO/IEC JTC 1/SC 25 - Interconnection of information technology equipmentrss
ICS35.200 - Interface and interconnection equipment
Pages399
File size2248 KB

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