IEC 62050:2005 Withdrawn

VHDL Register Transfer Level (RTL) synthesis

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Abstract

Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

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Additional information

Publication typeInternational Standard
Publication date2005-07-19
Withdrawal date2010-08-04
Edition1.0
Available language(s)English
TC/SCTC 91 - Electronics assembly technologyrss
ICS25.040.01 - Industrial automation systems in general
35.240.50 - IT applications in industry
Pages121
File size782 KB

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