IEC 63011-1:2018
Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
Abstract
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
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Additional information
| Publication type | International Standard |
|---|---|
| Publication date | 2018-11-28 |
| Edition | 1.0 |
| Available language(s) | English/French |
| TC/SC | TC 47/SC 47A - Integrated circuitsrss |
| ICS | 31.200 - Integrated circuits. Microelectronics |
| Stability date | 2024 |
| Pages | 24 |
| File size | 1332 KB |
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