IEC 63011-1:2018
Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
Abstract
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
Additional information
Publication type | International Standard |
---|---|
Publication date | 2018-11-28 |
Edition | 1.0 |
Available language(s) | English/French |
TC/SC | TC 47/SC 47A - Integrated circuitsrss |
ICS | 31.200 - Integrated circuits. Microelectronics |
Stability date | 2024 |
Pages | 24 |
File size | 1332 KB |
The following test report forms are related:
Share your publications
Learn how to share your publications with your colleagues, using networking options.
Payment information
Our prices are in Swiss francs (CHF). We accept all major credit cards (American Express, Mastercard and Visa, JCB and CUP), PayPal and bank transfers as form of payment.
Keep in touch
Keep up to date with new publication releases and announcements with our free IEC Just Published email newsletter.
Contact customer services
Please send your enquiry by email or call us on +41 22 919 02 11 between 09:00 – 16:00 CET Monday to Friday.