IEC 60822:1988
VSB - Parallel Sub-system Bus of the IEC 60821 VMEbus
Abstract
The VSB bus was designed to meet the needs of multiprocessor systems based on high-performance 32-bit microprocessors built up from board assemblies. lt includes a high-speed asynchronous data transfer bus allowing masters to direct the transfer of binary data to and from slaves according to 4 kinds of cycles: address-only, single-transfer, block-transfer and interrupt-acknowledge cycles. It also includes an arbitration bus enabling arbiter modules and/or requester modules to coordinate the use of the data-transfer bus according to two arbitration methods (series or parallel). Note: -For the price of this publication, please consult the ISO/IEC price-code list.
Additional information
Publication type | International Standard |
---|---|
Publication date | 1988-12-30 |
Edition | 1.0 |
Available language(s) | English/French |
TC/SC | ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipmentrss |
ICS | 31.080.01 - Semiconductor devices in general 35.200 - Interface and interconnection equipment 35.160 - Microprocessor systems |
Stability date | 2026 |
Pages | 311 |
File size | 11403 KB |
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