IEC 63011-3:2018 PRV 
Pre release version

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via

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Abstract

This Final Draft International Standard is an up to 6 weeks' pre-release of the official publication. It is available for sale during its voting period: 2018-08-31 to 2018-10-12. By purchasing this FDIS now, you will automatically receive, in addition, the final publication.

IEC 63011-3:2018 specifies a reference model of through-silicon via (TSV) electrical characteristics required for an interface design in three dimensional integrated circuit (3-D IC) to transmit and receive digital data and measurement conditions for resistance and capacitance to specify TSV characteristics in 3-D IC. Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the scope of this document.
 

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Additional information

Publication typeInternational Standard
Publication date2018-08-31
Edition1.0
Available language(s)English/French
TC/SCTC 47/SC 47A - Integrated circuitsrss
ICS31.200 - Integrated circuits. Microelectronics
Stability date  2024
Pages29
File size2630 KB

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