IEC 62530-2:2021 

SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual


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IEC 62530-2:2021(E) establishes the Universal Verification Methodology (UVM), a set of application programming
interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™. This publication has the status of a double logo IEC/IEEE standard.

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Additional information

Publication typeInternational Standard
Publication date2021-07-26
Available language(s)English
TC/SCTC 91 - Electronics assembly technologyrss
ICS25.040.01 - Industrial automation systems in general
35.060 - Languages used in information technology
Stability date  2026
File size5505 KB

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