SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™. This publication has the status of a double logo IEC/IEEE standard.
|Publication type||International Standard|
|TC/SC||TC 91 - Electronics assembly technologyrss|
|ICS||25.040.01 - Industrial automation systems in general|
35.060 - Languages used in information technology
|File size||5505 KB|
The following test report forms are related:
Share your publications
Learn how to share your publications with your colleagues, using networking options.
Our prices are in Swiss francs (CHF). We accept all major credit cards (American Express, Mastercard and Visa), PayPal and bank transfers as form of payment.
Keep in touch
Keep up to date with new publication releases and announcements with our free IEC Just Published email newsletter.
Contact customer services
Please send your enquiry by email or call us on +41 22 919 02 11 between 09:00 – 17:00 CET Monday to Friday.