SystemVerilog - Unified Hardware Design, Specification, and Verification Language
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.
|Publication type||International Standard|
|TC/SC||TC 91 - Electronics assembly technologyrss|
|ICS||25.040.01 - Industrial automation systems in general|
35.060 - Languages used in information technology
|File size||16348 KB|
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