IEC TR 62856:2013
Documentation on design automation subjects - The Bird's-eye View of Design Languages (BVDL)
Abstract
IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report:
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.
Additional information
Publication type | Technical Report |
---|---|
Publication date | 2013-08-07 |
Edition | 1.0 |
Available language(s) | English/French |
TC/SC | TC 91 - Electronics assembly technologyrss |
ICS | 25.040.01 - Industrial automation systems in general 35.240.50 - IT applications in industry |
Stability date | 2023 |
Pages | 42 |
File size | 1414 KB |
The following test report forms are related:
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