IEC 62530-2:2023
SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
Abstract
IEC 62530-2:2023 establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.1. This is an IEC/IEEE dual logo standard.
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Additional information
| Publication type | International Standard |
|---|---|
| Publication date | 2023-10-11 |
| Edition | 2.0 |
| Available language(s) | English |
| TC/SC | TC 91 - Electronics assembly technologyrss |
| ICS | 25.040.01 - Industrial automation systems in general 35.060 - Languages used in information technology |
| Stability date | 2028 |
| Pages | 457 |
| File size | 5130 KB |
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