IEC 62142:2005 Withdrawn
Verilog (R) register transfer level synthesis
Abstract
Defines a set of modeling rules for writing Verilog®
HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL
are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
Additional information
Publication type | International Standard |
---|---|
Publication date | 2005-06-27 |
Withdrawal date | 2010-08-04 |
Edition | 1.0 |
Available language(s) | English |
TC/SC | TC 91 - Electronics assembly technologyrss |
ICS | 25.040.99 - Other industrial automation systems |
Stability date | 2010 |
Pages | 109 |
File size | 622 KB |
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