IEC 62142:2005 Withdrawn

Verilog (R) register transfer level synthesis


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Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.

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Additional information

Publication typeInternational Standard
Publication date2005-06-27
Withdrawal date2010-08-04
Available language(s)English
TC/SCTC 91 - Electronics assembly technologyrss
ICS25.040.99 - Other industrial automation systems
File size622 KB

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